LMK5B33216集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

1 Features

? Ultra-low jitter BAW VCO based Ethernet clocks

– 43-fs typical/ 70-fs maximum RMS jitter at

312.5 MHz

– 50-fs typical/ 80-fs maximum RMS jitter at

156.25 MHz

? 3 high-performance Digital Phase Locked Loops

(DPLLs) with paired Analog Phase Locked Loops

(APLLs)

– Programmable DPLL LPF bandwidth from 10

mHz to 4 kHz

? 2 differential or single-ended DPLL inputs

– 1-Hz to 200-MHz, single-ended input frequency

– 5-MHz to 800-MHz, differential input frequency

– Digital holdover and hitless switching

? 16 outputs with programmable output formats

– 1-Hz to 1250-MHz output frequency with

HSDS/LVDS formats. Programmable swing and

common mode

– 25-MHz to 400-MHz output frequency with

HCSL format. PCIe Gen 1 to 5 compliant

– 1-Hz to 200-MHz LVCMOS outputs on OUT0

and OUT1

? I2C or 3-wire/4-wire SPI interface

?