M2V64S3DTP-7中文資料三菱電機數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

M2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit, M2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M2V64S20DTP, M2V64S30DTP and M2V64S40DTP achieve very high speed data rate up to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems.

FEATURES

- Single 3.3v±0.3V power supply

- Max. Clock frequency -6:133MHz, -7:100MHz, -8:100MHz

- Fully Synchronous operation referenced to clock rising edge

- 4 bank operation controlled by BA0 & BA1 (Bank Address)

- /CAS latency- 2 and 3 (programmable)

- Burst length- 1, 2, 4, 8 and full page (programmable)

- Burst type- sequential and interleave (programmable)

- Byte Control- DQML and DQMU for M2V64S40DTP

- Random column access

- Auto precharge and All bank precharge controlled by A10

- Auto refresh and Self refresh

- 4096 refresh cycles every 64ms

- LVTTL Interface

- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch