M48Z2M1V集成電路（IC）的存儲(chǔ)器規(guī)格書PDF中文資料

M48Z2M1V屬于集成電路（IC）的存儲(chǔ)器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的M48Z2M1V存儲(chǔ)器存儲(chǔ)器是集成電路上用作數(shù)據(jù)存儲(chǔ)設(shè)備的半導(dǎo)體器件。這些器件分為非易失性或易失性兩種，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、閃存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。這些器件的存儲(chǔ)容量為 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、單線、SPI、UFS、Xccela 總線和 1-線。

DESCRIPTION

The M48Z2M1/2M1Y ZEROPOWER? RAM is a non-volatile 16,777,216 bit Static RAM organized as 2,097,152 words by 8 bits. The device combines two internal lithium batteries, CMOS SRAMs and a control circuit in a plastic 36 pin DIP long Module.

■ INTEGRATED LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and

BATTERIES

■ CONVENTIONAL SRAM OPERATION;

UNLIMITED WRITE CYCLES

■ 10 YEARS of DATA RETENTION in the

ABSENCE of POWER

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES

(VPFD = Power-fail Deselect Voltage):

– M48Z2M1: 4.5V ≤ VPFD ≤ 4.75V

– M48Z2M1Y: 4.2V ≤ VPFD ≤ 4.50V

■ BATTERIES ARE INTERNALLY ISOLATED

UNTIL POWER IS APPLIED

■ PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 2Mb x 8 SRAMs