MB90V520A中文資料富士通數(shù)據(jù)手冊(cè)PDF規(guī)格書

■ DESCRIPTION

The MB90520A/520B series is a general-purpose 16-bit microcontroller designed for process control applications in consumer products that require high-speed real-time processing.

The microcontroller instruction set is based on the AT architecture of the F2MC* family with additional instructions for high-level languages, extended addressing modes, enhanced multiplication and division instructions, and a complete range of bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word (32-bit) data.

■ FEATURES

? Clock

? Internal PLL clock multiplication circuit

? Selectable machine clock (PLL clock) : Base oscillation divided by two or multiplied by one to four (For a 4 MHz base oscillation, the machine clock range is 4 MHz to 16 MHz) .

? Sub-clock (32.768 KHz) operation available

Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = ×4, VCC = 5.0 V)

? 16MB CPU memory space

Internal 24-bit addressing

? Instruction set optimized for controller applications

Rich data types (bit, byte, word, long-word)

Extended addressing modes (23 types)

Enhanced signed multiplication and division instructions and RETI instruction

Enhanced calculation precision using a 32-bit accumulator

? Instruction set designed for high-level language (C) and multi-tasking

System stack pointer

Enhanced pointer-indirect instructions and barrel shift instructions

? Faster execution speed

4-byte instruction queue

ROM mirror function (48 Kbytes of bank FF is mirrored in bank 00)

? Program patch function : An address match detection function (2 × addresses)

? Interrupt function

32 programmable interrupts with 8 levels

? Automatic data transmission function independent of CPU operation

Extended intelligent I/O service function (EI2OS) : Up to 16 channels

? Low-power consumption (stand-by) modes

Sleep mode (CPU operating clock stops, peripherals continue to operate.)

Pseudo-clock mode (Only oscillation clock and timebase timer continue to operate.)

Clock mode (Main oscillation clock stops, sub-clock and clock timer continue to operate.)

Stop mode (Main oscillation and sub-clock both stop.)

CPU intermittent operation mode

Hardware stand-by mode (Change to stop mpde by operating hardware stand-by pins.)

? Process

CMOS technology

? I/O ports

General-purpose I/O ports (CMOS input/output) : 53 ports

General-purpose I/O ports (inputs with pull-up resistors) : 24 ports

General-purpose I/O ports (Nch open-drain outputs) : 8 ports

? Timers

Timebase timer, clock timer, watchdog timer : 1 channel each

8/16-bit PPG timers 0 and 1 : 8-bit × 2 channels or 16-bit × 1 channel

16-bit reload timers 0 and 1 : 2 channels

16-bit I/O timers :

16-bit free-run timers 0 and 1 : 2 channels

16-bit input capture 0 : 2 channels (2 channels per unit)

16-bit output compare 0 and 1 : 8 channels (4 channels per unit)

8/16-bit up/down counter/timers 0 and 1 : 8-bit × 2 channels or 16-bit × 1 channel

Clock output function : 1 channel

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