MCM63P733ATQ117中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

The MCM63P733A is a 4M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC? and other high performance microprocessors. It is organized as 128K words of 32 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

The MCM63P733A operates from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible.

? MCM63P733A–133 = 4 ns Access/7.5 ns Cycle (133 MHz)

MCM63P733A–117 = 4.2 ns Access/8.5 ns Cycle (117 MHz)

MCM63P733A–100 = 4.5 ns Access/10 ns Cycle (100 MHz)

MCM63P733A–90 = 5 ns Access/11 ns Cycle (90 MHz)

? 3.3 V + 10/– 5 Core, Power Supply, 2.5 V or 3.3 V I/O Supply

? ADSP, ADSC, and ADV Burst Control Pins

? Selectable Burst Sequencing Order (Linear/Interleaved)

? Internally Self–Timed Write Cycle

? Byte Write and Global Write Control

? Single–Cycle Deselect

? Sleep Mode (ZZ)

? 100–Pin TQFP Package