MCM67T415中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

16K x 15 Bit Cache Tag RAM for Pentium? Processors

The MCM67T415 is a 245,760 bit cache–tag static RAM designed to support Pentium microprocessors at bus speeds up to 66 MHz. It is organized as 16K words of 15 bits each and is fabricated using Motorola‘s high performance, silicon gate BiCMOS technology. There are twelve common I/O tag bits and three separate I/O status bits. A 12–bit comparator is on–chip to allow fast comparison of the 12 stored tag bits with the current tag input data. An active high MATCH output is generated when the valid bit is true and these two groups of data are the same for a given address.

? 16K x 15 Configuration:

– 12 Tag Bits

– Three Status Bits (Valid, Dirty, and WT)

? Valid Bit used to Qualify Match Output

? High–Speed Address–to–Match Comparison Times – 9/10/12 ns

? BRDY Circuitry Included Inside the Cache–Tag for the Highest Speed Operation

? Asynchronous Read/Match Operation and Synchronous Write and Reset Operation

? Separate Write Enable for Tag Bits and Status Bits

? Separate Output Enable for Tag Bits, Status Bits, and BRDY

? Synchronous RESET Pin for Invalidation of all Tag Entries

? Dual Chip Selects for Easy Depth Expansion with No Performance Degradation

? I/O Pins Both 5 V TTL and 3.3 V LVTTL Compatible with VCCQ Pins

? PWRDN Pin to Place Device in Low–Power Mode

? Drop–In Replacement for IDT71215

? Packaged in an 80–Pin Thin Quad Flat Pack (TQFP)