首頁(yè)>MH16S64APHB-7>規(guī)格書(shū)詳情
MH16S64APHB-7中文資料三菱電機(jī)數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
| 廠商型號(hào) |
MH16S64APHB-7 |
| 功能描述 | 1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)Synchronous DRAM |
| 文件大小 |
688.94 Kbytes |
| 頁(yè)面數(shù)量 |
55 頁(yè) |
| 生產(chǎn)廠商 | Mitsubishi Electric Semiconductor |
| 企業(yè)簡(jiǎn)稱 |
Mitsubishi【三菱電機(jī)】 |
| 中文名稱 | 三菱電機(jī)株式會(huì)社官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-2-4 22:50:00 |
MH16S64APHB-7規(guī)格書(shū)詳情
DESCRIPTION
The MH16S64APHB is 16777216 - word by 64-bit Synchronous DRAM module. This consists of eight industry standard 16Mx8 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP.
The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required.
This is a socket type - memory modules, suitable for easy interchange or addition of modules.
FEATURES
? Utilizes industry standard 16M x 8 Sy nchronous DRAMs TSOP and industry standard EEPROM in TSSOP
? 168-pin (84-pin dual in-line package)
? single 3.3V±0.3V power supply
? Max. Clock frequency -6:133MHz,-7,8:100MHz
? Fully synchronous operation referenced to clock rising edge
? 4 bank operation controlled by BA0,1(Bank Address)
? /CAS latency- 2/3(programmable)
? Burst length- 1/2/4/8/Full Page(programmable)
? Burst type- sequential / interleave(programmable)
? Column access - random
? Auto precharge / All bank precharge controlled by A10
? Auto refresh and Self refresh
? 4096 refresh cycle /64ms
? LVTTL Interface
? Discrete IC and module design conform to PC100/PC133 specification.
APPLICATION
PC main memory
產(chǎn)品屬性
- 型號(hào)：
MH16S64APHB-7
- 制造商：
MITSUBISHI
- 制造商全稱：
Mitsubishi Electric Semiconductor
- 功能描述：
1,073,741,824-BIT(16,777,216 - WORD BY 64-BIT)Synchronous DRAM
