首頁(yè)>MH8S64AQFC-8L>規(guī)格書(shū)詳情
MH8S64AQFC-8L中文資料三菱電機(jī)數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
| 廠商型號(hào) |
MH8S64AQFC-8L |
| 功能描述 | 536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM |
| 文件大小 |
672.81 Kbytes |
| 頁(yè)面數(shù)量 |
55 頁(yè) |
| 生產(chǎn)廠商 | Mitsubishi Electric Semiconductor |
| 企業(yè)簡(jiǎn)稱(chēng) |
Mitsubishi【三菱電機(jī)】 |
| 中文名稱(chēng) | 三菱電機(jī)株式會(huì)社官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-1-8 9:01:00 |
MH8S64AQFC-8L規(guī)格書(shū)詳情
DESCRIPTION
The MH8S64AQFC is 8388608 - word by 64-bit Synchronous DRAM module. This consists of four industry standard 8Mx16 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP.
The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required.
This is a socket type - memory modules, suitable for easy interchange or addition of modules.
? Utilizes industry standard 8M x 16 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
? 144-pin (72-pin dual in-line package)
? single 3.3V±0.3V power supply
? Max. Clock frequency -6:133MHz,-7,8:100MHz
? Fully synchronous operation referenced to clock rising edge
? 4 bank operation controlled by BA0,1(Bank Address)
? /CAS latency- 2/3(programmable)
? Burst length- 1/2/4/8/Full Page(programmable)
? Burst type- sequential / interleave(programmable)
? Column access - random
? Auto precharge / All bank precharge controlled by A10
? Auto refresh and Self refresh
? 4096 refresh cycle /64ms
? LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
MITSUBISHI |
23+ |
NA |
25060 |
只做進(jìn)口原裝,終端工廠免費(fèi)送樣 |
詢(xún)價(jià) |
