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MT5C1009CW-35/XT中文資料AUSTIN數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

MT5C1009CW-35/XT
廠(chǎng)商型號(hào)

MT5C1009CW-35/XT

功能描述

128K x 8 SRAM WITH CHIP & OUTPUT ENABLE

文件大小

254.43 Kbytes

頁(yè)面數(shù)量

17 頁(yè)

生產(chǎn)廠(chǎng)商 Austin Semiconductor
企業(yè)簡(jiǎn)稱(chēng)

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中文名稱(chēng)

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更新時(shí)間

2025-1-25 10:20:00

MT5C1009CW-35/XT規(guī)格書(shū)詳情

GENERAL DESCRIPTION

The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle.

For design flexibility in high-speed memory applications, this device offers chip enable (CE) and output enable (OE) features. These enhancements can place the outputs in High-Z for additional flexibility in system design.

The “L” version offers a 2V data retention mode, reducing current consumption to 2mW maximum.

All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. It is particularly well suited for use in high-density, high-speed system applications.

FEATURES

? Access Times: 15, 20, 25, 35, 45, 55 and 70 ns

? Battery Backup: 2V data retention

? Low power standby

? High-performance, low-power CMOS process

? Single +5V (+10) Power Supply

? Easy memory expansion with CE and OE options.

? All inputs and outputs are TTL compatible

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24+
5000
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ASI
18+
NA
300
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MICROSS
15+
32CSOJ.405
50
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ASI
24+
CLCC32
27
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ASI
23+
NA
50000
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ASI
2021+
60000
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ASI
23+
CDIP32
14960
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56520
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80000
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MCT
1995
100
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