NAND512W4M5BZC5E中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

Summary description

The NAND256-M, NAND512-M and NAND01G-M are Multi-Chip Packages which combine up to 512 Mbit LPSDRAM with a 256 Mbit, 512 Mbit or 1 Gbit NAND Flash memory. This combination of LPSDRAM and NAND Flash can result in up to 1 Gbit of memory.

Features

■ Multi-Chip Packages

– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND Flash + 1 die of 256 Mb (x16) SDR LPSDRAM

– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND Flash + 2 dice of 256 Mb (x16) SDR LPSDRAMs

– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND Flash +1 die of 256 Mb (x16) DDR LPSDRAM

– 1 die of 512 Mb (x16) NAND Flash + 1 die of 256 Mb or 512 Mb (x16) DDR LPSDRAM

■ Supply voltages

– VDDF = 1.7V to 1.95V or 2.5V to 3.6V

– VDDD = VDDQD = 1.7V to 1.9V

■ Electronic Signature

■ ECOPACK? packages

■ Temperature range

– -30 to 85°C

Flash Memory

■ NAND Interface

– x8 or x16 bus width

– Multiplexed Address/ Data

■ Page size

– x8 device: (512 + 16 spare) Bytes

– x16 device: (256 + 8 spare) Words

■ Block size

– x8 device: (16K + 512 spare) Bytes

– x16 device: (8K + 256 spare) Words

■ Page Read/Program

– Random access: 15μs (max)

– Sequential access: 50ns (min)

– Page program time: 200μs (typ)

■ Copy Back Program mode

– Fast page copy without external buffering

■ Fast Block Erase

– Block erase time: 2ms (typ)

■ Status Register

■ Data integrity

– 100,000 Program/Erase cycles

– 10 years Data Retention

LPSDRAM

■ Interface: x16 or x 32 bus width

■ Deep Power Down mode

■ 1.8v LVCMOS interface

■ Quad internal Banks controlled by BA0 and BA1

■ Automatic and controlled Precharge

■ Auto Refresh and Self Refresh

– 8,192 Refresh cycles/64ms

– Programmable Partial Array Self Refresh

– Auto Temperature Compensated Self Refresh

■ Wrap sequence: sequential/interleave

■ Burst Termination by Burst Stop command and Precharge command