PCA9541APW/03集成電路（IC）的專用規(guī)格書PDF中文資料

General description

The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual master I2C-bus applications where system operation is required, even when one master fails or the controller card is removed for maintenance. The two masters (for example, primary and back-up) are located on separate I2C-buses that connect to the same downstream I2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are used to select one master at a time. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and will not affect communication between the on-line master and the slave devices on the downstream I2C-bus.

Features

2-to-1 bidirectional master selector

I2C-bus interface logic; compatible with SMBus standards

PCA9541A/01 powers up with Channel 0 selected

PCA9541A/03 powers up with no channel selected and either master can take control of the bus

Active LOW interrupt input

2 active LOW interrupt outputs

Active LOW reset input

4 address pins allowing up to 16 devices on the I2C-bus

Channel selection via I2C-bus

Bus initialization/recovery function

Bus traffic sensor

Low Ronswitches

Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses

No glitch on power-up

Supports hot insertion

Software identical for both masters

Low standby current

Operating power supply voltage range of 2.3 V to 5.5 V 6.0 V tolerant inputs

0 Hz to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: SO16, TSSOP16, HVQFN16

Applications

High reliability systems with dual masters

Gatekeeper multiplexer on long single bus

Bus initialization/recovery for slave devices without hardware reset

Allows masters without arbitration logic to share resources