PM7351中文資料PMC數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The PM7351 S/UNI-VORTEX is a monolithic integrated circuit typically used with its sister device, the S/UNI-DUPLEX, to implement a point-to-point serial backplane interconnect architecture.

FEATURES

? Integrated analog/digital device that interfaces a high speed parallel bus to 8 bidirectional data streams, each transported over a high speed Low Voltage Differential Signal (LVDS) serial link.

? Works with its sister device, the S/UNI-DUPLEX, to satisfy a full set of system level requirements for backplane interconnect:

? Transports user data by providing the inter-card data-path.

? Inter-processor communication by providing an integrated inter-card control channel.

? Exchanges flow control information (back-pressure) to prevent data loss.

? Provides embedded command and control signals across the backplane: system reset, error indications, protection switching commands, etc.

? Clock/timing distribution (system clocks as well as reference clocks such as 8 kHz timing references).

? Fault detection, redundancy, protection switching, and inserting/removing cards while the system is running (hot swap).

? Each S/UNI-VORTEX Interfaces to 8 S/UNI-DUPLEX devices (via the LVDS links) to create a point-to-multipoint serial backplane architecture.

? Up to 16 S/UNI-VORTEX devices (interfacing to a maximum of 128 S/UNIDUPLEXs) can reside on a single system bus.

? In the LVDS receive direction: accepts cell streams from the 8 LVDS links, multiplexing them into a single cell stream which is presented to the system bus as a single Utopia L2 compatible PHY.

? In the LVDS transmit direction: receives cell streams from the bus master, and routes the cells to the appropriate serial link.

? Cell read/write to the 8 LVDS links is available via the microprocessor port. Provides optional hardware assisted CRC32 calculation across cells to create an embedded inter-processor communication channel across the LVDS links.

? Optionally routes the embedded control channels from the 8 links to/ from the system bus.

? Under software control, the 8 LVDS links can be individually marked active or standby. This is used by the far end S/UNI-DUPLEXs to implement 1:1 protected systems.

? Error monitoring and cell counting on all links.

? Requires no external memories.

? Low power 3.3V CMOS technology.

? Standard 5 pin P1149 JTAG port.

? 304 ball SBGA, 31mm x 31mm.

APPLICATIONS

? Single shelf or multi-shelf Digital Subscriber Loop Access Multiplexer (DSLAM).

? ATM, frame relay, IP switch.

? Multiservice access multiplexer.

? Universal Mobile Telecommunication System (UMTS) wireless base stations.

? UMTS wireless base station controllers.

? Multi-shelf access concentrators.