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QL2009-0PB256I規(guī)格書(shū)詳情
[QuickLogic]
PRODUCT SUMMARY
The QL2009 is a 9,000 usable ASIC gate,16,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.
FEATURES
Ultimate Verilog/VHDL Silicon Solution
- Abundant, high-speed interconnect eliminates manual routing
- Flexible logic cell provides high efficiency and performance
- Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
- 16-bit counter speeds exceeding 200 MHz
- 9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os
- 3-layer metal ViaLink? process for small die sizes
- 100 routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
- Complex functions (up to 16 inputs) in a single logic cell
- High synthesis gate utilization from logic cell fragments
- Full IEEE Standard JTAG boundary scan capability
- Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
- 3.3V and 5.0V operation with low standby power
- I/O pin-compatibility between different devices in the same packages
- PCI compliant (at 5.0V), full speed 33 MHz implementations
- High design security provided by security fuses
Total of 225 I/O Pins
- 217 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz
產(chǎn)品屬性
- 型號(hào):
QL2009-0PB256I
- 功能描述:
3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
QUICKLOGTC |
QFP |
899933 |
集團(tuán)化配單-有更多數(shù)量-免費(fèi)送樣-原包裝正品現(xiàn)貨-正規(guī) |
詢(xún)價(jià) | |||
QUICKLOGIC |
22+ |
QFP208 |
1152 |
⊙⊙新加坡大量現(xiàn)貨庫(kù)存,深圳常備現(xiàn)貨!歡迎查詢(xún)!⊙ |
詢(xún)價(jià) | ||
QUICKLOG |
QFP |
53650 |
一級(jí)代理 原裝正品假一罰十價(jià)格優(yōu)勢(shì)長(zhǎng)期供貨 |
詢(xún)價(jià) | |||
QUALCOMM |
23+ |
TQFP |
1001 |
全新原裝現(xiàn)貨 |
詢(xún)價(jià) | ||
QUALCOMM |
23+ |
TQFP |
2870 |
絕對(duì)全新原裝!現(xiàn)貨!特價(jià)!請(qǐng)放心訂購(gòu)! |
詢(xún)價(jià) | ||
QUALCOMM |
23+ |
TQFP |
4500 |
全新原裝、誠(chéng)信經(jīng)營(yíng)、公司現(xiàn)貨銷(xiāo)售 |
詢(xún)價(jià) | ||
QUALCOMM |
2138+ |
TQFP |
8960 |
專(zhuān)營(yíng)BGA,QFP原裝現(xiàn)貨,假一賠十 |
詢(xún)價(jià) | ||
QUICKLOGIC |
2023+ |
QFP |
50000 |
原裝現(xiàn)貨 |
詢(xún)價(jià) | ||
20+ |
QFP |
500 |
樣品可出,優(yōu)勢(shì)庫(kù)存歡迎實(shí)單 |
詢(xún)價(jià) | |||
QUALCOMM |
16+ |
QFP |
985 |
進(jìn)口原裝現(xiàn)貨/價(jià)格優(yōu)勢(shì)! |
詢(xún)價(jià) |