QL3025-0PQ208M中文資料etc未分類制造商數(shù)據(jù)手冊(cè)PDF規(guī)格書

[QUICK LOGIC]

Product Summary

The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.

Device Highlights

High Performance and High Density

■60,000 Usable PLD Gates with 316 I/Os

■16-bit counter speeds over 300 MHZ, data path speeds over 400 MHz

■0.35um four-layer metal non-volatile CMOS process for smallest die sizes

Easy to Use/Fast Development Cycles

■100 routable with 100 utilization and complete pin-out stability

■Variable-grain logic cells provide high performance and 100 utilization

■Comprehensive design tools include high quality Verilog/VHDL synthesis

Advanced I/O Capabilities

■Interfaces with both 3.3 volt and 5.0 volt devices

■PCI compliant with 3.3V and 5.0V buses for -1/-2 speed grades

■Full JTAG boundary scan

■Registered I/O cells with individually controlled clocks and output enables

Features

Total of 180 I/O pins

■308 bidirectional input/output pins, PCI-compliant for 5.0 volt and 3.3 volt buses for -1/-2 speed grades

■8 high-drive input/distributed network pins Eight Low-Skew Distributed Networks

■Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs - each

driven by an input-only pin

■Up to six global clock/control networks available to the logic cell F1, clock, set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback High Performance

■Input + logic cell + output total delays under 6 ns

■Data path speeds exceeding 400 MHz

■Counter speeds over 300 MHz