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SN54SC4T32-SEP中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書
廠商型號(hào) |
SN54SC4T32-SEP |
功能描述 | SN54SC4T32-SEP Radiation Tolerant, Quadruple 2-Input Positive-OR Gates With Integrated Translation |
文件大小 |
1.76168 Mbytes |
頁面數(shù)量 |
20 頁 |
生產(chǎn)廠商 | Texas Instruments |
企業(yè)簡(jiǎn)稱 |
TI【德州儀器】 |
中文名稱 | 美國(guó)德州儀器公司官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-1-6 22:30:00 |
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1 Features
? Vendor item drawing available, VID
V62/23629-01XE
? Total ionizing dose characterized at 30 krad (Si)
– Total ionizing dose radiation lot acceptance
testing (TID RLAT) for every wafer lot to 30
krad (Si)
? Single-event effects (SEE) characterized:
– Single event latch-up (SEL) immune to linear
energy transfer (LET) = 43 MeV-cm2 /mg
– Single event transient (SET) characterized to
43 MeV-cm2 /mg
? Wide operating range of 1.2 V to 5.5 V
? Single-supply translating gates at 5/3.3/2.5/1.8/1.2
V VCC
– TTL compatible inputs:
? Up translation:
– 1.8-V – Inputs from 1.2 V
– 2.5-V – Inputs from 1.8 V
– 3.3-V – Inputs from 1.8 V, 2.5 V
– 5.0-V – Inputs from 2.5 V, 3.3 V
? Down translation:
– 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V,
5.0 V
– 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
– 2.5-V – Inputs from 3.3 V, 5.0 V
– 3.3-V – Inputs from 5.0 V
? 5.5 V tolerant input pins
? Output drive up to 25 mA AT 5-V
? Latch-up performance exceeds 250 mA per
JESD 17
? Space enhanced plastic (SEP)
– Controlled baseline
– Gold bondwire
– NiPdAu lead finish
– One assembly and test site
– One fabrication site
– Military (–55°C to 125°C) temperature range
– Extended product life cycle
– Product traceability
– Meets NASAs ASTM E595 outgassing
specification
2 Applications
? Enable or disable a digital signal
? Controlling an indicator LED
? Translation between communication modules and
system controllers
3 Description
The SN54SC4T32-SEP contains four independent
2-input OR Gates with Schmitt-trigger inputs and
extended voltage operation to allow for level
translation. Each gate performs the Boolean function
Y = A + B in positive logic. The output level is
referenced to the supply voltage (VCC) and supports
1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to
support up translation for lower voltage CMOS inputs
(for example 1.2 V input to 1.8 V output or 1.8 V input
to 3.3 V output). Additionally, the 5-V tolerant input
pins enable down translation (for example 3.3 V to 2.5
V output).
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
TI |
2020+ |
DIP |
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DLZ |
22+ |
CDIP14 |
354000 |
詢價(jià) | |||
TI |
23+ |
CDIP14 |
3000 |
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TI |
23+ |
NA |
320 |
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TI |
2018+ |
26976 |
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TI/TEXAS |
23+ |
原廠封裝 |
8931 |
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23+ |
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66800 |
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8650 |
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TI |
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369 |
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詢價(jià) | ||
TI |
0827+;0513+ |
DIP |
127 |
詢價(jià) |