SPC5643LF0VLQ1中文資料飛思卡爾數(shù)據(jù)手冊(cè)PDF規(guī)格書

Overview

This document provides electrical specifications, pin assignments, and package diagrams for the MPC5643L series of microcontroller units (MCUs). For functional characteristics, refer to the MPC5643L Microcontroller Reference Manual. For use of the MPC5643Lin a fail-safe system according to safety standard IEC 61508, refer to the MPC5643L Safety Application Guide. The MPC5643L series microcontrollers are system-on-chip devices that are built on Power Architecture? technology and:

? Are 100 user-mode compatible with the classic Power Architecture instruction set

? Contain enhancements that improve the architecture’s fit in embedded applications

? Include additional instruction support for digital signal processing (DSP)

? Integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system

This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices.

MPC5643L Microcontroller

? High-performance e200z4d dual core

– 32-bit Power Architecture? Book E CPU

– Core frequency as high as 120 MHz

– Dual issue five-stage pipeline core

– Variable Length Encoding (VLE)

– Memory Management Unit (MMU)

– 4 KB instruction cache with error detection code

– Signal processing engine (SPE)

? Memory available

– 1 MB Flash memory with ECC

– Built-in RWW capabilities for EEPROM emulation

– As much as 128 KB on-chip RAM with ECC

? SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection

– Sphere of replication (SoR) for key components (such as CPU core, DMA, crossbar switch)

– Fault collection and control unit (FCCU)

– Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU

– Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware

– Boot-time Built-In Self-Test for ADC and flash memory triggered by software

– Replicated safety enhanced watchdog

– Replicated junction temperature sensor

– Non-maskable interrupt (NMI)

– 16-region memory protection unit (MPU)

– Clock monitoring units (CMU)

– Power management unit (PMU)

– Cyclic redundancy check (CRC) unit

? Decoupled Parallel mode for high performance use of replicated cores

? Nexus Class 3+ interface

? Interrupts

– Replicated 16-priority controller

– Replicated 16-channel eDMA controller

? GPIOs individually programmable as input, output or

special function

? Three 6-channel general-purpose eTimer units

? Two FlexPWM units

– Four 16-bit channels per module

? Communications interfaces

– Two LINFlex channels

– Three DSPI channels with automatic chip select generation

– Two FlexCAN interfaces (2.0B Active) with 32 message objects – FlexRay module (V2.1) with dual channel, up to 64 message objects and speed as fast as 10 Mbit/s

? Two 12-bit analog-to-digital converters (ADCs)

– 16 input channels

– Programmable cross triggering unit (CTU) to synchronize ADCs conversion with timer and PWM

? Sine wave generator (D/A with low pass filter)

? On-chip CAN/UART/FlexRay Bootstrap loader

? Single 3.0 V to 3.6 V voltage supply

? Ambient temperature range –40 °C to 125 °C

? Junction temperature range –40 °C to 150 °C