TC51V8512ATR-12中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The TC51V8512AF is a 4M bit high speed CMOS pseudo static RAM organized as 524,288 words by 8 bits. The TC51V8512AF

utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power

storage. The TC51V8512AF operates from a single 3.0V power supply. Refreshing is supported by a refresh (OE/RFSH) input which

enables two types of refreshing - auto refresh and self refresh. The TC51V8512AF features a static RAM-like interface with a write

cycle in which the input data is written into the memory cell at the rising edge of R/W thus simplifying the microprocessor interface.

The TC51V8512AF is available in a 32-pin small outline plastic flat package, and a thin small outline package (forward type,

reverse type).

Features

? Organization: 524,288 words x 8 bits

? Low voltage function: 3.0V±10

Data retention supply voltage: 2.0V - 3.3V

Fast access time

ICEA CE Access Time

TOEA OE Access Time

tac Cycle Time

Power Dissipation

Self Refresh Current 3.0V

TC51V8512AF Family

-15

150ns

80ns

230ns

66mW

-12

120ns

60ns

190ns

99mW

40μA

Auto refresh is supported by an internal refresh address

counter

Self refresh is supported by an internal timer

Inputs and outputs TTL compatible

Refresh: 2048 refresh cycles/32ms

Package

- TC51V8512AF: SOP32-P-525

- TC51V8512AFT: TSOP32-P-400

- TC518V512ATR: TSOP32-P-400A