TC74AC112P中文資料東芝數(shù)據(jù)手冊PDF規(guī)格書

Dual J-K Flip Flop with Preset and Clear

The TC74AC112 is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology.

It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.

Features

? High speed: fmax = 170 MHz (typ.) at VCC = 5 V

? Low power dissipation: ICC = 4 μA (max) at Ta = 25°C

? High noise immunity: VNIH = VNIL = 28 VCC (min)

? Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.

? Balanced propagation delays: tpLH ～ ? tpHL

? Wide operating voltage range: VCC (opr) = 2 to 5.5 V

? Pin and function compatible with 74F112