UPD160040A中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

FEATURES

? CMOS level input

? 384 outputs

? Input of 8 bits (gray scale data) by 6 dots

? Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter

? Logic power supply voltage (VDD1): 2.5 to 3.6 V

? Driver power supply voltage (VDD2): 12.5 to 15.5 V (switchable, VSEL)

? High-speed data transfer: fCLK = 55 MHz MAX. (internal data transfer speed when operating at 3.0 V ≤ VDD1 ≤ 3.6 V)

= 40 MHz MAX. (internal data transfer speed when operating at 2.5 V ≤ VDD1 < 3.0 V)

? Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V

? Apply for dot-line inversion, n-line inversion and column line inversion

? Output voltage polarity inversion function (POL)

? Output inversion function (POL21, POL 22)

? Output reset control is possible (MODE)

? Slew-rate control is possible (SRC)

? Output resistance control is possible (ORC)

? Single bank arrangement is possible (Loaded with slim TCP)