UPD16742N-XXX中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

FEATURES

· CMOS level input

· 384-output channel

· Input of 8 bits (gradation data) by 6 dots

· Capable of outputting 256 values by means of 11 external power modules and a D/A converter (C-DAC)

· Output dynamic range VSS2 + 0.1 V to VDD2 – 0.1 V

· Logic Part Power Supply Voltage (VDD1) : 3.3 ± 0.3 V

· Driver Part Power Supply Voltage (VDD2) : 9.0 ± 0.5 V

· High-speed data transfer: fMAX. = 65 MHz (internal data transfer speed when operating at VDD1 = 3.0 V)

· Apply for dot-line inversion, n-line inversion and column line inversion

· Output voltage polarity reverse is possible (POLA)

· Input data reverse function is incorporated (POLB (O/E))

· Output offset for different eight values can be controlled by offset signals (three signals)