UPD72850BGK-9EU中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM)

? Full P1394a draft 2.1 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset,

multi-speed concatenation, arbitration acceleration, fly-by concatenation

? Fully compliant with OHCI requirements

? Package: 80-pin plastic TQFP

? Data rate: 400/200/100 Mbps

? Supports PHY pinging and remote PHY access packets

? 3.3 V single power supply

? 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency

? Electrically isolated Link interface

? Support LPS/Link-on as part of PHY/Link interface

? Extended Resume signaling for compatibility with legacy DV devices

? System power management by signaling of node power class information

? Cable power monitor (CPS) is equipped

? Number of supported port are selectable

? 1port, 2port, 3port. This selection is only under Suspend/Resume Off mode

? Pin Compatibility with MD8405E (FUJIFILM MICRODEVICES CO., LTD)