UPD72862中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0

? Compliant with protocol enhancement as defined in P1394a draft 2.0

? Modular 32-bit host interface compliant to PCI Specification release 2.1

? Supports PCI-Bus Power Management Interface Specification release 1.0

? Supports Cardbus

? Equipped CIS register

? Cycle Master and Isochronous Resource Manager capable

? Compatible to PHY Layer implementation of 100/200/400 Mbps via 2/4/8-bit data interface

? Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048 bytes)

? 32-bit CRC generation and checking for receive/transmit packets

? 4-isochronous transmit DMAs and 4-isochronous receive DMAs supported

? Support both IEEE1394-1995 compliant PHY and P1394a compliant PHY

? Internal control and operational registers direct-mapped to PCI configuration space

? 2-wire Serial EEPROMTM interface supported