UT8R512K815UPC中文資料AEROFLEX數(shù)據(jù)手冊PDF規(guī)格書

INTRODUCTION

The UT8R512K8 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by active LOW and HIGH chip enables (E1, E2), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90 when deselected.

Writing to the device is accomplished by taking chip enable one (E1) input LOW, chip enable two (E2) HIGH and write enable (W) input LOW. Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip enable one (E1) and output enable (G) LOW while forcing write enable (W) and chip enable two (E2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

FEATURES

? 15ns maximum access time

? Asynchronous operation for compatibility with industry standard 512K x 8 SRAMs

? CMOS compatible inputs and output levels, three-state bidirectional data bus

- I/O Voltage 3.3 volts, 1.8 volt core

? Operational environment:

- Intrinsic total-dose: 300K rad(Si)

- SEL Immune >100 MeV-cm2/mg

- LETth (0.25): 53.0 MeV-cm2/mg

- Memory Cell Saturated Cross Section 1.67E-7cm2/bit

- Neutron Fluence: 3.0E14n/cm2

- Dose Rate

- Upset 1.0E9 rad(Si)/sec

- Latchup >1.0E11 rad(Si)/sec

? Packaging options:

- 36-lead ceramic flatpack (3.762 grams)

? Standard Microcircuit Drawing 5962-03235

- QML Q & Vcompliant part