V53C8129H中文資料茂矽電子數(shù)據(jù)手冊PDF規(guī)格書

Description

The V53C8129H is a high speed 131,072 x 8 bit CMOS dynamic random access memory. The V53C8129H offers a combination of features: EDO Page Mode for high data bandwidth, fast usable speed, CMOS standby current.

All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Page Mode with extended data out operation allows random access of up to 256 columns (x8) bits within a row with cycle times as short as 14 ns. Because of static circuitry, the CAS clock is not in the critical timing path. The flow-through column address latches allow address pipelining while relaxing many critical system timing requirements for fast usable speed. These features make the V53C8129H ideally suited for graphics, digital signal processing and high performance peripherals.

Features

■ 128K x 8-bit organization

■ RAS access time: 35, 40, 45, 50 ns

■ EDO Page Mode supports sustained I/O data rates up to 71.5 MHz

■ Low power dissipation

? V53C8129H-50

— Operating Current: 135 mA max

— TTL Standby Current: 2.0 mA max

■ Low CMOS Standby Current: 1.0 mA max

■ Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability

■ Refresh Interval: 512 cycles/8 ms

■ Available in 26/24 pin 300 mil SOJ package