VG36128801A中文資料VML數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The device is CMOS Synchronous Dynamic RAM organized as 8,388,608 - word x 4 -bit x 4 - bank, 4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. These various organizations provide wide choice for different applications. It is designed with the state-of-the-art technology to meet standard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the performance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.

Features

? Single 3.3V (±0.3V) power supply

? High speed clock cycle time : 7.5ns/10ns

? Fully synchronous with all signals referenced to a positive clock edge

? Programmable CAS Iatency (2,3)

? Programmable burst length (1,2,4,8,& Full page)

? Programmable wrap sequence (Sequential/Interleave)

? Automatic precharge and controlled precharge

? Auto refresh and self refresh modes

? Quad Internal banks controlled by BA0 & BA1 (Bank select)

? Each Bank can be operated simultaneously and independently

? I/O level : LVTTL compatible

? Random column access in every cycle

? x4, x8, x16 organization

? Input/Output controlled by DQM ( LDQM, UDQM )

? 4,096 refresh cycles/64ms

? Burst termination by burst stop and precharge command

? Burst read/single write option