VQ100分立半導(dǎo)體產(chǎn)品的晶體管-FETMOSFET-單個(gè)規(guī)格書PDF中文資料
| 廠商型號(hào) |
VQ100 |
| 參數(shù)屬性 | VQ100 包裝為管件；類別為分立半導(dǎo)體產(chǎn)品的晶體管-FETMOSFET-單個(gè)；產(chǎn)品描述：MOSFET N-CH 60V 0.4A TO-205 |
| 功能描述 | Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology |
| 文件大小 |
10.50173 Mbytes |
| 頁(yè)面數(shù)量 |
212 頁(yè) |
| 生產(chǎn)廠商 | Microsemi Corporation |
| 企業(yè)簡(jiǎn)稱 |
Microsemi【美高森美】 |
| 中文名稱 | 美高森美公司官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-4-29 10:31:00 |
| 人工找貨 | VQ100價(jià)格和庫(kù)存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
VQ100規(guī)格書詳情
Features and Benefits
High Capacity
? 15 k to 1 M System Gates
? Up to 144 kbits of True Dual-Port SRAM
? Up to 300 User I/Os
Reprogrammable Flash Technology
? 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
? Instant On Level 0 Support
? Single-Chip Solution
? Retains Programmed Design when Powered Off
High Performance
? 350 MHz System Performance
? 3.3 V, 66 MHz 64-Bit PCI?
In-System Programming (ISP) and Security
? ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM?-enabled ProASIC?3 devices) via JTAG (IEEE 1532–compliant)?
? FlashLock? to Secure FPGA Contents
Low Power
? Core Voltage for Low Power
? Support for 1.5 V-Only Systems
? Low-Impedance Flash Switches
High-Performance Routing Hierarchy
? Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
? 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
? 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
? Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
? Bank-Selectable I/O Voltages—up to 4 Banks per Chip
? Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X? and LVCMOS 2.5 V / 5.0 V Input
? Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
? I/O Registers on Input, Output, and Enable Paths
? Hot-Swappable and Cold Sparing I/Os?
? Programmable Output Slew Rate? and Drive Strength
? Weak Pull-Up/-Down
? IEEE 1149.1 (JTAG) Boundary Scan Test
? Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL?
? Six CCC Blocks, One with an Integrated PLL
? Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
? Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory?
? 1 kbit of FlashROM User Nonvolatile Memory
? SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)?
? True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
? M1 ProASIC3 Devices—ARM?Cortex?-M1 Soft Processor Available with or without Debug
產(chǎn)品屬性
- 產(chǎn)品編號(hào)：
VQ1004P-2
- 制造商：
Vishay Siliconix
- 類別：
分立半導(dǎo)體產(chǎn)品 > 晶體管 - FET，MOSFET - 單個(gè)
- 包裝：
管件
- 驅(qū)動(dòng)電壓（最大 Rds On，最小 Rds On）：
5V，10V
- Vgs（最大值）：
±20V
- 描述：
MOSFET N-CH 60V 0.4A TO-205
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
VISHAY |
18+ |
原廠原裝假一賠十 |
216 |
原廠很遠(yuǎn)現(xiàn)貨很近,找現(xiàn)貨選星佑電子,原廠原裝假一賠 |
詢價(jià) | ||
siliconix |
05+ |
DIP14 |
14180 |
只做原廠原裝,認(rèn)準(zhǔn)寶芯創(chuàng)配單專家 |
詢價(jià) | ||
Vishay Siliconix |
22+ |
14DIP |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價(jià) | ||
DG/SIL |
24+ |
DIP |
350 |
詢價(jià) | |||
VISHAY |
24+ |
N/A |
6800 |
一級(jí)代理商進(jìn)口原裝現(xiàn)貨、價(jià)格合理 |
詢價(jià) | ||
VISHAY |
24+ |
200 |
全新原裝 |
詢價(jià) | |||
BB |
20+ |
DIP14 |
67500 |
原裝優(yōu)勢(shì)主營(yíng)型號(hào)-可開原型號(hào)增稅票 |
詢價(jià) | ||
SILICONIX |
25+ |
DIP14 |
1981 |
⊙⊙新加坡大量現(xiàn)貨庫(kù)存,深圳常備現(xiàn)貨!歡迎查詢!⊙ |
詢價(jià) | ||
SIL |
24+ |
CDIP |
200 |
進(jìn)口原裝正品優(yōu)勢(shì)供應(yīng) |
詢價(jià) | ||
VISHAY/威世 |
2022+ |
200 |
只做原裝,價(jià)格優(yōu)惠,長(zhǎng)期供貨。 |
詢價(jià) |
