W9864G6DB中文資料華邦電子數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

W9864G6DB is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1M words × 4 banks × 16 bits. Using pipelined architecture and 0.175 μm process technology, W9864G6DB delivers a data bandwidth of up to 286M bytes per second (-7).

W9864G6DB -7.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9864G6DB is ideal for main memory in high performance applications.

FEATURES

? 2.7V ? 3.6V power supply

? 1048576 words × 4 banks × 16 bits organization

? Self refresh current: Standard and low power

? CAS latency: 2 and 3

? Burst Length: 1, 2, 4, 8, and full page

? Sequential and Interleave burst

? Burst read, single write operation

? Byte data controlled by DQM

? Power-down Mode

? Auto-precharge and controlled precharge

? 4K refresh cycles/ 64 mS

? Interface: LVTTL

? Packaged in BGA 60 balls pitch = 0.65 mm, using PB free materials