WED2ZLRSP01S50BC中文資料WEDC數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256K x 32.

FEATURES

■ Fast clock speed: 166, 150, 133, and 100MHz

■ Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns

■ Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns

■ Single +2.5V ± 5 power supply (VCC)

■ Snooze Mode for reduced-standby power

■ Individual Byte Write control

■ Clock-controlled and registered addresses, data I/Os and control signals

■ Burst control (interleaved or linear burst)

■ Packaging:

■ 209-bump BGA package

■ Low capacitive bus loading