WED3DL328V8BC中文資料WEDC數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION

The WED3DL328V is an 8Mx32 Synchronous DRAM configured as 4x2Mx32. The SDRAM BGA is constructed with two 8Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 119 lead, 14mm by 22mm, BGA.

FEATURES

■ 53 Space Savings vs. Monolithic Solution

■ Reduced System Inductance and Capacitance

■ Pinout and Footprint Compatible to SSRAM 119 BGA

■ 3.3V Operating Supply Voltage

■ Fully Synchronous to Positive Clock Edge

■ Clock Frequencies of 133MHZ, 125MHZ and 100MHZ

■ Burst Operation

■ Sequential or Interleave

■ Burst Length = Programmable 1, 2, 4, 8 or Full Page

■ Burst Read and Write

■ Multiple Burst Read and Single Write

■ Data Mask Control Per Byte

■ Auto and Self Refresh

■ Automatic and Controlled Precharge Commands

■ Suspend Mode and Power Down Mode

■ 119 Pin BGA, JEDEC MO-163