XAM6754AKGHIAMW中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

1 Features

Processor Cores:

? Up to Quad 64-bit Arm? Cortex?-A53

microprocessor subsystem at up to 1.4GHz

– Quad-core Cortex-A53 cluster with 512KB L2

shared cache with SECDED ECC

– Each A53 core has 32KB L1 DCache with

SECDED ECC and 32KB L1 ICache with Parity

protection

? Single-core Arm? Cortex?-R5F at up to 800MHz,

integrated as part of MCU Channel with FFI

– 32KB ICache, 32KB L1 DCache, and 64KB

TCM with SECDED ECC on all memories

– 512KB SRAM with SECDED ECC

? Single-core Arm? Cortex?-R5F at up to 800MHz,

integrated to support Device Management

– 32KB ICache, 32KB L1 DCache, and 64KB

TCM with SECDED ECC on all memories

? Single-core Arm? Cortex?-R5F at up to 800MHz,

integrated to support Run-time Management

– 32KB ICache, 32KB L1 DCache, and 64KB

TCM with SECDED ECC on all memories

? Two Deep Learning Accelerators (up to 4 TOPS

total), each with:

– C7x floating point, up to 40 GFLOPS, 256-bit

Vector DSP at up to 1.0GHz

– Matrix Multiply Accelerator (MMA), up to 2

TOPS (8b) at up to 1.0GHz

– 32KB L1 DCache with SECDED ECC and

64KB L1 ICache with Parity protection

– 2.25MB of L2 SRAM with SECDED ECC

? Depth and Motion Processing Accelerators

(DMPAC)

– Dense Optical Flow (DOF) Accelerator

– Stereo Disparity Engine (SDE) Accelerator

? Vision Processing Accelerators (VPAC) with Image

Signal Processor (ISP) and multiple vision assist

accelerators:

– 600MP/s ISP

– Support for 12-bit RGB-IR

– Support for up to 16-bit input RAW format

– Line support up to 4096

– Wide Dynamic Range (WDR), Lens Distortion

Correction (LDC), Vision Imaging Subsystem

(VISS), and Multi-Scalar (MSC) support

? Output color format : 8-bits, 12-bits, and

YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

? Display subsystem

– Triple display support over OLDI/LVDS (1x

OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI

? OLDI-SL (Single Link): up to 1920 x 1080 at

60fps (165-MHz Pixel Clock)

? OLDI-DL (Dual Link): up to 3840 x 1080 at

60fps (150-MHz Pixel Clock)

? MIPI? DSI: with 4 Lane MIPI? D-PHY

supports up to 3840 x 1080 at 60fps (300-

MHz Pixel Clock)

? DPI (24-bit RGB parallel interface): up to

1920 x 1080 at 60fps (165-MHz pixel clock)

– Four display pipelines with hardware overlay

support. A maximum of two display pipelines

may be used per display.

– Supports safety features such as freeze frame

detection and data correctness check

? 3D Graphics Processing Unit

– IMG BXS-4-64 with 256KB cache

– Up to 50 GFLOPS

– Single shader core

– OpenGL ES3.2 and Vulkan 1.2 API support

? Four Camera Serial Interface (CSI-2) Receiver

with 4 Lane D-PHY

– MIPI? CSI-2 v1.3 Compliant + MIPI? D-PHY

1.2

– CSI-RX supports for 1,2,3, or 4 data lane mode

up to 2.5Gbps per lane

? One CSI2.0 Transmitter with 4 Lane D-PHY

(shared with MIPI DSI)

– CSI-TX supports for 1,2, or 4 data lane mode

up to 2.5Gbps per lane

? Video Encoder/Decoder

– Support for HEVC (H.265) Main profiles at

Level 5.1 High-tier

– Support for H.264 BaseLine/Main/High Profiles

at Level 5.2

– Support for up to 4K UHD resolution

(3840 × 2160)

? Up to 400MP/s operation

? Motion JPEG encode at 416MPixels/s with

resolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

? On-chip RAM dedicated to key processing cores

– 256KB of On-Chip RAM (OCRAM) with

SECDED ECC

– 256KB of On-Chip RAM with SECDED ECC in

SMS Subsystem

– 512KB of On-chip RAM with SECDED ECC in

Cortex-R5F MCU Subsystem

– 64KB of On-chip RAM with SECDED ECC in

R5F Device Manager Subsystem

– 64KB of On-chip RAM with SECDED ECC in

R5F Run-Time Manager Subsystem

– 2.25MB of L2 SRAM with SECDED ECC in

each C7x Deep Learning Accelerator (up to

4.5MB total)

? DDR Subsystem (DDRSS)

– Supports LPDDR4 memory types

– 32-bit data bus with inline ECC

– Supports speeds up to 4000MT/s

– Max LPDDR4 size of 8GB

Functional Safety:

? Functional Safety-Compliant targeted (on select

part numbers)

– Developed for functional safety applications

– Documentation will be available to aid IEC

61508 functional safety system design

– Systematic capability up to SIL 3 targeted

– Hardware Integrity up to SIL 2 targeted

– Safety-related certification

? IEC 61508 planned

Security:

? Secure boot supported

– Hardware-enforced Root-of-Trust (RoT)

– Support to switch RoT via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

? Trusted Execution Environment (TEE) supported

– Arm TrustZone? based TEE

– Extensive firewall support for isolation

– Secure watchdog/timer/IPC

– Secure storage support

– Replay Protected Memory Block (RPMB)

support

? Dedicated Security Controller with user

programmable HSM core and dedicated security

DMA & IPC subsystem for isolated processing

? Cryptographic acceleration supported

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

? Supports cryptographic cores

– AES – 128-/192-/256-Bit key sizes

– SHA2 – 224-/256-/384-/512-Bit key sizes

– DRBG with true random number generator

– PKA (Public Key Accelerator) to Assist in

RSA/ECC processing for secure boot

? Debugging security

– Secure software controlled debug access

– Security aware debugging

High-Speed Interfaces:

? PCI-Express? Gen3 single lane controller (PCIE)

– Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3

(8.0GT/s) operation with auto-negotiation

? Integrated Ethernet switch supporting (total 2

external ports)

– RMII(10/100) or RGMII (10/100/1000) or SGMII

(1Gbps)

– IEEE1588 (Annex D, Annex E, Annex F with

802.1AS PTP)

– Clause 45 MDIO PHY management

– Packet Classifier based on ALE engine with

512 classifiers

– Priority based flow control

– Time Sensitive Networking (TSN) support

– Four CPU H/W interrupt Pacing

– IP/UDP/TCP checksum offload in hardware

? USB3.1-Gen1 Port

– One enhanced SuperSpeed Gen1 port

– Port configurable as USB host, USB peripheral,

or USB Dual-Role Device

– Integrated USB VBUS detection

? USB2.0 Port

– Port configurable as USB host, USB peripheral,

or USB Dual-Role Device (DRD mode)

– Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

? 9x Universal Asynchronous Receiver-Transmitters

(UART)

? 5x Serial Peripheral Interface (SPI) controllers

? 7x Inter-Integrated Circuit (I2C) ports

? 5x Multichannel Audio Serial Ports (McASP)

? General-Purpose I/O (GPIO), All LVCMOS I/O can

be configured as GPIO

? 4x Controller Area Network (CAN) modules with

CAN-FD support

Media and Data Storage:

? 3x Secure Digital? (SD?) (4b+4b+8b) interfaces

– 1x 8-bit eMMC interface up to HS400 speed

– 2x 4-bit SD/SDIO interfaces up to UHS-I

– Compliant with eMMC 5.1, SD 3.0, and SDIO

Version 3.0

? 1× General-Purpose Memory Controller (GPMC)

up to 133MHz

? OSPI/QSPI with DDR / SDR support

– Support for Serial NAND and Serial NOR Flash

– 4GBytes memory address support

– XIP mode with optional on-the-fly encryption

Technology / Package:

? 16-nm FinFET technology

? 18 mm x 18 mm, 0.65 mm pitch with VCA (AMW)

Companion Power Management Solution:

? Functional Safety-Compliant support up to ASIL-B

or SIL-2 targeted

? TPS6522x PMIC

? TPS6287x Stackable, Fast Transient Bucks

2 Applications

? Human Machine Interface (HMI)

? Hospital patient monitoring

? Industrial PC

? Building security system

? Off-highway vehicle

? Test and measurement

? Energy storage systems

? Video Surveillance

? Machine Vision

? Industrial mobile robot (AGV/AMR)

? Front camera systems

3 Description

The AM67x scalable processor family is based on the evolutionary Jacinto? 7 architecture, targeted at Smart

Vision Camera and General Compute applications and built on extensive market knowledge accumulated over

a decade of TI’s leadership in the Vision processor market. The AM67x family is built for a broad set of

cost-sensitive high performance compute applications in Factory Automation, Building Automation, and other

markets.

The AM67x provides high performance compute technology for both traditional and deep learning algorithms

at industry leading power/performance ratios with a high level of system integration to enable scalability and

lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for

general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional

algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and MCU cores. All

protected by industrial-grade security hardware accelerators.

AM67x contains up to four Arm? Cortex?-A53 cores with 64-bit architecture, a Vision Processing Accelerator

(VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense

Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex?-R5F MCU Island core and two Cortex?-

R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements

necessary for Linux applications as well as the implementation of traditional vision computing based algorithms.

Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader

sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics

applications. Key cores include two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA”

deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS

within the lowest power envelope in the industry when operating at the typical automotive worst case junction

temperature of 125°C.

The AM67x integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with

one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included

in AM67x to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI,

CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM67x supports secure boot for IP

protection with the built-in HSM (Hardware Security Module) and employs advanced power management support

for power-sensitive applications.