AD9524BCPZ-REEL7集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)規(guī)格書PDF中文資料

AD9524BCPZ-REEL7屬于集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9524BCPZ-REEL7應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。

GENERAL DESCRIPTION

The AD9524 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz. The AD9524 is defined to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise require ments necessary for acceptable data converter SNR performance.

FEATURES

Output frequency: <1 MHz to 1 GHz

Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)

Zero delay operation

Input-to-output edge timing: <±150 ps

6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS

6 dedicated output dividers with jitter-free adjustable delay

Adjustable delay: 63 resolution steps of ? period of VCO output divider

Output-to-output skew: <±50 ps

Duty-cycle correction for odd divider settings

Automatic synchronization of all outputs on power-up

Absolute output jitter: <200 fs at 122.88 MHz

Integration range: 12 kHz to 20 MHz

Distribution phase noise floor: ?160 dBc/Hz

Digital lock detect

Nonvolatile EEPROM stores configuration settings

SPI- and I2C-compatible serial control port

Dual PLL architecture

PLL1

Low bandwidth for reference input clock cleanup with external VCXO

Phase detector rate of 300 kHz to 75 MHz

Redundant reference inputs

Auto and manual reference switchover modes

Revertive and nonrevertive switching

Loss of reference detection with holdover mode

Low noise LVCMOS output from VCXO used for RF/IF synthesizers

PLL2

Phase detector rate of up to 250 MHz

Integrated low noise VCO

APPLICATIONS

LTE and multicarrier GSM base stations

Wireless and broadband infrastructure

Medical instrumentation

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols

Forward error correction (G.710)

High performance wireless transceivers

ATE and high performance instrumentation