GTLP36T612G中文資料仙童半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

General Description

The GTLP36T612 is an 36-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (

Features

■ Bidirectional interface between GTLP and LVTTL logic levels

■ Designed with edge rate control circuitry to reduce output noise on the GTLP port

■ Partitioned as two 18-Bit transceivers with individual latch timing and output control

■ VREF pin provides external supply reference voltage for receiver threshold adjustibility

■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature

■ TTL compatible driver and control inputs

■ Designed using Fairchild advanced BiCMOS technology

■ Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs

■ Power up/down and power off high impedance for live insertion

■ Open drain on GTLP to support wired-or connection

■ Flow through pinout optimizes PCB layout

■ D-type flip-flop, latch and transparent data paths

■ A Port source/sink ?24mA/+24mA

■ B Port sink +50mA

■ For more information see AN-5026, Using BGA Packages