IDT72V36104集成電路（IC）的FIFO存儲器規(guī)格書PDF中文資料

DESCRIPTION

The IDT72V3684/72V3694/72V36104 are designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic, high-speed, low-power, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations.

FEATURES

? Memory storage capacity:

IDT72V3684 – 16,384 x 36 x 2

IDT72V3694 – 32,768 x 36 x 2

IDT72V36104 – 65,536 x 36 x 2

? Clock frequencies up to 100 MHz (6.5ns access time)

? Two independent clocked FIFOs buffering data in opposite directions

? Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRB flag functions)

? Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024 )

? Serial or parallel programming of partial flags

? Retransmit Capability

? Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)

? Big- or Little-Endian format for word and byte bus sizes

? Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings

? Mailbox bypass registers for each FIFO

? Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)

? Auto power down minimizes power dissipation

? Available in space saving 128-pin Thin Quad Flatpack (TQFP)

? Pin compatible to the lower density parts, IDT72V3624/72V3634/ 72V3644/72V3654/72V3664/72V3674

? Industrial temperature range (–40°C to +85°C) is available