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ISPLSI2032-135LJI中文資料萊迪思數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

ISPLSI2032-135LJI
廠商型號(hào)

ISPLSI2032-135LJI

功能描述

In-System Programmable High Density PLD

文件大小

145.5 Kbytes

頁(yè)面數(shù)量

15 頁(yè)

生產(chǎn)廠商 Lattice Semiconductor
企業(yè)簡(jiǎn)稱(chēng)

Lattice萊迪思

中文名稱(chēng)

萊迪思半導(dǎo)體公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-5 9:16:00

ISPLSI2032-135LJI規(guī)格書(shū)詳情

Description

The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032 and 2032A feature 5V in system programmability and in-system diagnostic capabilities. The ispLSI 2032 and 2032A offer nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

Features

? ENHANCEMENTS

— ispLSI 2032A is Fully Form and Function Compat to the ispLSI 2032, with Identical Timing Specifcations and Packaging

— ispLSI 2032A is Built on an Advanced 0.35 Micron E2CMOS? Technology

? HIGH DENSITY PROGRAMMABLE LOGIC

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

? HIGH PERFORMANCE E2CMOS? TECHNOLOGY

— fmax = 180 MHz Maximum Operating Frequency

— tpd = 5.0 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100 Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

? IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP?) 5V Only

— Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyp

? OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBIL OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine G Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global Interconnectivity

產(chǎn)品屬性

  • 型號(hào):

    ISPLSI2032-135LJI

  • 制造商:

    Rochester Electronics LLC

  • 功能描述:

    - Bulk

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