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ISPLSI2064VL-135LJ44中文資料萊迪思數(shù)據(jù)手冊(cè)PDF規(guī)格書

ISPLSI2064VL-135LJ44
廠商型號(hào)

ISPLSI2064VL-135LJ44

功能描述

2.5V In-System Programmable SuperFAST??High Density PLD

文件大小

188.06 Kbytes

頁面數(shù)量

14

生產(chǎn)廠商 Lattice Semiconductor
企業(yè)簡(jiǎn)稱

Lattice萊迪思

中文名稱

萊迪思半導(dǎo)體公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2024-11-18 10:17:00

ISPLSI2064VL-135LJ44規(guī)格書詳情

Description

The ispLSI 2064VL is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP).

Features

? SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 64 and 32 I/O Pin Versions, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100 Functional, JEDEC and Pinout Compatible with

ispLSI 2064V and 2064VE Devices

? 2.5V LOW VOLTAGE 2064 ARCHITECTURE

— Interfaces with Standard 3.3V TTL Devices (Inputs

and I/Os are 3.3V Tolerant)

— 60 mA Typical Active Current

? HIGH-PERFORMANCE E2CMOS? TECHNOLOGY

— fmax = 165MHz Maximum Operating Frequency

— tpd = 5.5ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100 Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

? IN-SYSTEM PROGRAMMABLE

— 2.5V In-System Programmability (ISP?) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-OR

or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-toMarket

and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

? 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE

? THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

? ispDesignEXPERT? – LOGIC COMPILER AND COMPLETE

ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER?

— PC and UNIX Platforms

產(chǎn)品屬性

  • 型號(hào):

    ISPLSI2064VL-135LJ44

  • 功能描述:

    CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000B

  • RoHS:

  • 制造商:

    Lattice

  • 存儲(chǔ)類型:

    EEPROM

  • 大電池?cái)?shù)量:

    128

  • 最大工作頻率:

    333 MHz

  • 延遲時(shí)間:

    2.7 ns

  • 可編程輸入/輸出端數(shù)量:

    64

  • 工作電源電壓:

    3.3 V

  • 最大工作溫度:

    + 90 C

  • 最小工作溫度:

    0 C

  • 封裝/箱體:

    TQFP-100

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