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ISPLSI2064VL-135LJ44規(guī)格書詳情
Description
The ispLSI 2064VL is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP).
Features
? SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100 Functional, JEDEC and Pinout Compatible with
ispLSI 2064V and 2064VE Devices
? 2.5V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 3.3V TTL Devices (Inputs
and I/Os are 3.3V Tolerant)
— 60 mA Typical Active Current
? HIGH-PERFORMANCE E2CMOS? TECHNOLOGY
— fmax = 165MHz Maximum Operating Frequency
— tpd = 5.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100 Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
? IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP?) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket
and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
? 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE
? THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
? ispDesignEXPERT? – LOGIC COMPILER AND COMPLETE
ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER?
— PC and UNIX Platforms
產(chǎn)品屬性
- 型號(hào):
ISPLSI2064VL-135LJ44
- 功能描述:
CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000B
- RoHS:
否
- 制造商:
Lattice
- 存儲(chǔ)類型:
EEPROM
- 大電池?cái)?shù)量:
128
- 最大工作頻率:
333 MHz
- 延遲時(shí)間:
2.7 ns
- 可編程輸入/輸出端數(shù)量:
64
- 工作電源電壓:
3.3 V
- 最大工作溫度:
+ 90 C
- 最小工作溫度:
0 C
- 封裝/箱體:
TQFP-100
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
LETTICE |
22+ |
QFP |
2250 |
100%全新原裝公司現(xiàn)貨供應(yīng)!隨時(shí)可發(fā)貨 |
詢價(jià) | ||
LATTICE |
22+ |
80LT |
4860 |
品牌專業(yè)分銷商,可以零售 |
詢價(jià) | ||
LATTICE |
21+ |
QFP |
10000 |
原裝現(xiàn)貨假一罰十 |
詢價(jià) | ||
23+ |
原廠封裝 |
9888 |
專做原裝正品,假一罰百! |
詢價(jià) | |||
Lattice |
16+ |
原廠封裝 |
10000 |
全新原裝正品,代理優(yōu)勢(shì)渠道供應(yīng),歡迎來電咨詢 |
詢價(jià) | ||
Lattice |
24+ |
QFP |
66 |
詢價(jià) | |||
LATTICE |
2023+ |
QFP |
50000 |
原裝現(xiàn)貨 |
詢價(jià) | ||
LATTICE/萊迪斯 |
23+ |
QFP |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
LATTICE/萊迪斯 |
23+ |
QFP |
3000 |
一級(jí)代理原廠VIP渠道,專注軍工、汽車、醫(yī)療、工業(yè)、 |
詢價(jià) | ||
LATTICE |
24+ |
FPGA |
6309 |
原裝現(xiàn)貨 |
詢價(jià) |