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K4H511638A-TCA0中文資料三星數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
K4H511638A-TCA0規(guī)格書(shū)詳情
Features
? Double-data-rate architecture; two data transfers per clock cycle
? Bidirectional data strobe(DQS)
? Four banks operation
? Differential clock inputs(CK and CK)
? DLL aligns DQ and DQS transition with CK transition
? MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
? All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
? Data I/O transactions on both edges of data strobe
? Edge aligned data output, center aligned data input
? LDM,UDM/DM for write masking only
? Auto & Self refresh
? 15.6us refresh interval(4K/64ms refresh)
? Maximum burst refresh cycle : 8
? 66pin TSOP II package
產(chǎn)品屬性
- 型號(hào)：
K4H511638A-TCA0
- 制造商：
SAMSUNG
- 制造商全稱：
Samsung semiconductor
- 功能描述：
128Mb DDR SDRAM
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
SAMSUNG/三星 |
19+ |
BGA |
12731 |
進(jìn)口原裝現(xiàn)貨 |
詢價(jià) | ||
SAMSUNG/三星 |
2020+ |
NA |
80000 |
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開(kāi)13%增 |
詢價(jià) | ||
SAMSUNG |
23+ |
TSSOP |
28000 |
原裝正品 |
詢價(jià) | ||
SAMSUNG |
22+23+ |
TSSOP |
37580 |
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價(jià) | ||
SAMSUNG |
589220 |
16余年資質(zhì) 絕對(duì)原盒原盤 更多數(shù)量 |
詢價(jià) | ||||
SAMSUNG |
22+ |
TSSOP |
8000 |
原裝正品支持實(shí)單 |
詢價(jià) | ||
SAN |
23+ |
QFP |
3200 |
全新原裝、誠(chéng)信經(jīng)營(yíng)、公司現(xiàn)貨銷售 |
詢價(jià) | ||
SAMSUN |
23+ |
SSOP |
5500 |
現(xiàn)貨,全新原裝 |
詢價(jià) | ||
K4H511638B-TCB0 |
100 |
100 |
詢價(jià) | ||||
SAMSANG |
19+ |
TSSOP |
256800 |
原廠代理渠道,每一顆芯片都可追溯原廠； |
詢價(jià) |
