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M5M4V64S30ATP-10中文資料三菱電機(jī)數(shù)據(jù)手冊(cè)PDF規(guī)格書
| 廠商型號(hào) |
M5M4V64S30ATP-10 |
| 功能描述 | 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM |
| 文件大小 |
1.09639 Mbytes |
| 頁(yè)面數(shù)量 |
48 頁(yè) |
| 生產(chǎn)廠商 | Mitsubishi Electric Semiconductor |
| 企業(yè)簡(jiǎn)稱 |
Mitsubishi【三菱電機(jī)】 |
| 中文名稱 | 三菱電機(jī)株式會(huì)社官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-2-13 12:07:00 |
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DESCRIPTION
The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S30ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 125MHz /100MHz
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Burst Write / Single Write (programmable)
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A8
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
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|---|---|---|---|---|---|---|---|
MIT |
23+ |
TSOP54 |
8000 |
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3600 |
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SOP |
2789 |
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4275 |
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