PEB20571中文資料英飛凌數(shù)據(jù)手冊(cè)PDF規(guī)格書
PEB20571規(guī)格書詳情
Addendum to “DELIC Clock System Synchronization”
The DELIC Clock System Synchronization is described in the DELIC-LC PEB 20570/DELIC-PB PEB 20571 Data Sheet, independent of the version (2.1 .. 3.1).
As an addendum to chapter “DELIC Clock System Synchronization” of the DELICLC/DELIC-PB Data Sheet the following describes the system behaviour when using the VIP PEB 20590 or PEB 20591 in LT-T mode, for example when synchronizing to the Central Office.
When the Central Office is activated, its clock signal is retrieved by the RxPLL of the VIP and a 1.536 MHz reference signal is generated and used as input signal for the DELIC DCXO (pin XCLK). This signal is divided down to 8 kHz and used as input for the DCXO phase detector (PD). The second input to PD is another 8 kHz signal which originates from the 16.384 MHz output of the DCXO.
The DELIC PLL multiplies the 16.384 MHz DCXO signal up to 61.44 MHz. A divider generates the 15.36 MHz layer 1 clock which is used to clock the VIP.
產(chǎn)品屬性
- 型號(hào):
PEB20571
- 制造商:
INFINEON
- 制造商全稱:
Infineon Technologies AG
- 功能描述:
DSP Embedded Line and Port Interface Controller
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---|---|---|---|---|---|---|---|
Infineon(英飛凌) |
23+ |
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2020+ |
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19526 |
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詢價(jià) | |||
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TQFP100 |
3000 |
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詢價(jià) | ||
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23+ |
標(biāo)準(zhǔn)封裝 |
7000 |
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