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PLL102-109規(guī)格書詳情
DESCRIPTIONS
The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purposes by strapping AVDD to ground.
FEATURES
? PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.
? Distributes one clock Input to one bank of six differential outputs.
? Track spread spectrum clocking for EMI reduction.
? Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by programming CLKINT and FBOUT skew channel, or from –1.1ns to +3.5ns if additional DDR skew channels are enabled.
? Two independent programmable DDR skew channels from –0.3ns to +0.4ns with step size ±100ps.
? Support 2-wire I2C serial bus interface.
? 2.5V Operating Voltage.
? Available in 28-Pin 209mil SSOP.
產(chǎn)品屬性
- 型號：
PLL102-109
- 制造商：
PLL
- 制造商全稱：
PLL
- 功能描述：
Programmable DDR Zero Delay Clock Driver
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
PHASELIN |
20+ |
SSOP48 |
30 |
進口原裝現(xiàn)貨,假一賠十 |
詢價 | ||
16+ |
FBGA |
4000 |
進口原裝現(xiàn)貨/價格優(yōu)勢! |
詢價 | |||
PHASELI |
2020+ |
SSOP48 |
30 |
百分百原裝正品 真實公司現(xiàn)貨庫存 本公司只做原裝 可 |
詢價 | ||
PHASELINK |
23+ |
SSOP |
89630 |
當(dāng)天發(fā)貨全新原裝現(xiàn)貨 |
詢價 | ||
PHASELIN |
2023+ |
SSOP48 |
8800 |
正品渠道現(xiàn)貨 終端可提供BOM表配單。 |
詢價 | ||
PHASELIN |
24+ |
NA/ |
30 |
優(yōu)勢代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價 | ||
PHASELI |
24+ |
SSOP48 |
8000 |
只做自己庫存,全新原裝進口正品假一賠百,可開13%增 |
詢價 | ||
PHASELIN |
0350+ |
SSOP48 |
30 |
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價 | ||
PHASELIN |
20+ |
TSSOP8 |
2960 |
誠信交易大量庫存現(xiàn)貨 |
詢價 | ||
23+ |
BGAQFP |
8659 |
原裝公司現(xiàn)貨!原裝正品價格優(yōu)勢. |
詢價 |
