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SN74LS112D

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

TheSN54/74LS112AdualJKflip-flopfeaturesindividualJ,K,clock,andasynchronoussetandclearinputstoeachflip-flop.WhentheclockgoesHIGH,theinputsareenabledanddatawillbeaccepted.ThelogicleveloftheJandKinputsmaybeallowedtochangewhentheclockpulseisHIGHandthe

MotorolaMotorola, Inc

摩托羅拉加爾文制造公司

SN74LS112D

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

TITexas Instruments

德州儀器美國(guó)德州儀器公司

74LS112

DualJ-KNegative-edge-triggeredFlip-Flops(withPresetandClear)

●Quadrupie2-InputPositiveNANDGates ●Quadruple2-InputPositiveNANDGates(withOpenCollectorOutput) (Continue....)

HitachiHitachi Semiconductor

日立日立公司

74LS112

DUALJ-KNEGATIVE-EDGE-TRIGGEREDFLIP-FLOPSWITHPRESETANDCLEAR

TITexas Instruments

德州儀器美國(guó)德州儀器公司

74LS112

DUALJKNEGATIVEEDGE-TRIGGEREDFLIP-FLOP

TheSN54/74LS112AdualJKflip-flopfeaturesindividualJ,K,clock,andasynchronoussetandclearinputstoeachflip-flop.WhentheclockgoesHIGH,theinputsareenabledanddatawillbeaccepted.ThelogicleveloftheJandKinputsmaybeallowedtochangewhentheclockpulseisHIGHandthe

MotorolaMotorola, Inc

摩托羅拉加爾文制造公司

74LS112

DualNegative-Edge-TriggeredMaster-SlaveJ-KFlip-FlopwithPreset,Clear,andComplementaryOutputs

GeneralDescription Thisdevicecontainstwoindependentnegative-edge-triggeredJ-Kflip-flopswithcomplementaryoutputs.TheJandKdataisprocessedbytheflip-floponthefallingedgeoftheclockpulse.Theclocktriggeringoccursatavoltagelevelandisnotdirectlyrelatedtothetra

FairchildFairchild Semiconductor

仙童半導(dǎo)體飛兆/仙童半導(dǎo)體公司

74LS112A

DUALJKNEGATIVEEDGE-TRIGGEREDFLIP-FLOP

MotorolaMotorola, Inc

摩托羅拉加爾文制造公司

74LS112A

DualNegative-Edge-TriggeredMaster-SlaveJ-KFlip-FlopwithPreset,Clear,andComplementaryOutputs

GeneralDescription Thisdevicecontainstwoindependentnegative-edge-triggeredJ-Kflip-flopswithcomplementaryoutputs.TheJandKdataisprocessedbytheflip-floponthefallingedgeoftheclockpulse.Theclocktriggeringoccursatavoltagelevelandisnotdirectlyrelatedtothetra

FairchildFairchild Semiconductor

仙童半導(dǎo)體飛兆/仙童半導(dǎo)體公司

DM74LS112A

DualNegative-Edge-TriggeredMaster-SlaveJ-KFlip-FlopwithPreset,Clear,andComplementaryOutputs

GeneralDescription Thisdevicecontainstwoindependentnegative-edge-triggeredJ-Kflip-flopswithcomplementaryoutputs.TheJandKdataisprocessedbytheflip-floponthefallingedgeoftheclockpulse.Theclocktriggeringoccursatavoltagelevelandisnotdirectlyrelatedtothetra

FairchildFairchild Semiconductor

仙童半導(dǎo)體飛兆/仙童半導(dǎo)體公司

DM74LS112A

DUALNEGATIVE-EDGE-TRIGEREDMASTER-SLAVEJ-KFLIP-FLOPSWITHPRESET,CLEAR,ANDCOMPLEMENTARYOUTPUTS

NSCNational Semiconductor (TI)

美國(guó)國(guó)家半導(dǎo)體美國(guó)國(guó)家半導(dǎo)體公司

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MOT
24+
SMD
2427
本站庫(kù)存
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MOT
24+
SOP3.9
2987
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SN74LS112J
10
10
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TI
02+/03+
DIP
5262
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TI
2016+
DIP
6528
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TI
24+
DIP16
6800
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TI/MOTO
23+
DIP
5000
原裝正品,假一罰十
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TI　
24+
DIP
16800
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TI
24+
DIP
6430
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TI/德州儀器
23+
DIP
50000
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更多SN74LS112D供應(yīng)商 更新時(shí)間2025-3-11 16:00:00

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