V53C8258H50中文資料茂矽電子數(shù)據(jù)手冊PDF規(guī)格書

Description

The V53C8258H is a high speed 262,144 x 8 bit CMOS dynamic random access memory. The V53C8258H offers a combination of features: Page Mode with Extended Data Output for high data bandwidth, and Low CMOS standby current.

All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Page Mode with Extended Data Output operation allows random access of up to 512 (x8) bits within a row with cycle times as fast as 14 ns. Because of static circuitry, the CAS clock is not in the critical timing path. The flow-through column address latches allow address pipelining while relaxing many critical system timing requirements. The V53C8258H is ideally suited for graphics, digital signal processing and high-performance computing systems.

Features

■ 256K x 8-bit organization

■ EDO Page Mode for a sustained data rate of 71 MHz

■ RAS access time: 35, 40, 45, 50 ns

■ Low power dissipation

■ Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability

■ Refresh Interval: 512 cycles/8 ms

■ Available in 24 pin 300 mil Plastic DIP, 26/24 pin 300 mil SOJ and 28-pin 300 mil TSOP-I packages

■ Single 5V±10 Power Supply

■ TTL Interface