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ISPLSI2032-80LJ中文資料萊迪思數(shù)據(jù)手冊PDF規(guī)格書
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ISPLSI2032-80LJ規(guī)格書詳情
Description
The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032 and 2032A feature 5V in system programmability and in-system diagnostic capabilities. The ispLSI 2032 and 2032A offer nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
Features
? ENHANCEMENTS
— ispLSI 2032A is Fully Form and Function Compat to the ispLSI 2032, with Identical Timing Specifcations and Packaging
— ispLSI 2032A is Built on an Advanced 0.35 Micron E2CMOS? Technology
? HIGH DENSITY PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
? HIGH PERFORMANCE E2CMOS? TECHNOLOGY
— fmax = 180 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100 Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
? IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP?) 5V Only
— Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyp
? OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBIL OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine G Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global Interconnectivity
產(chǎn)品屬性
- 型號:
ISPLSI2032-80LJ
- 功能描述:
CPLD - 復雜可編程邏輯器件 USE ispMACH 4000V
- RoHS:
否
- 制造商:
Lattice
- 存儲類型:
EEPROM
- 大電池數(shù)量:
128
- 最大工作頻率:
333 MHz
- 延遲時間:
2.7 ns
- 可編程輸入/輸出端數(shù)量:
64
- 工作電源電壓:
3.3 V
- 最大工作溫度:
+ 90 C
- 最小工作溫度:
0 C
- 封裝/箱體:
TQFP-100
供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
LATTICE/萊迪斯 |
23+ |
PLCC44 |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價 | ||
Lattice(萊迪斯) |
23+ |
特價 |
6000 |
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價 | ||
Lattice |
2021+ |
PLCC44 |
6800 |
原廠原裝,歡迎咨詢 |
詢價 | ||
LATTICE |
24+ |
PLCC44 |
16800 |
絕對原裝進口現(xiàn)貨,假一賠十,價格優(yōu)勢!? |
詢價 | ||
LATTICE |
24+ |
FPGA |
4621 |
原裝現(xiàn)貨 |
詢價 | ||
LATTICE |
22+ |
PLCC |
8200 |
全新進口原裝現(xiàn)貨 |
詢價 | ||
LATTICE |
2020+ |
PLCC44 |
80000 |
只做自己庫存,全新原裝進口正品假一賠百,可開13%增 |
詢價 | ||
LAT |
23+ |
65480 |
詢價 | ||||
LATTICE/萊迪斯 |
22+ |
plcc |
11190 |
原裝正品 |
詢價 | ||
LATT |
05+ |
原廠原裝 |
4483 |
只做全新原裝真實現(xiàn)貨供應 |
詢價 |