MT41J64M16JT-125G中文資料鎂光數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

MT41J256M4 – 32 Meg x 4 x 8 banks

MT41J128M8 – 16 Meg x 8 x 8 banks

MT41J64M16 – 8 Meg x 16 x 8 banks

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins.