DSP56301PW100中文資料恩智浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

Features

? 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V

? Object code compatible with the DSP56000 core with highly parallel instruction set

? Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-

Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream

generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support

under software control

? Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes

optimized for DSP applications (including immediate offsets), internal instruction cache

controller, internal memory-expandable hardware stack, nested hardware DO loops, and fast

auto-return interrupts

? Direct Memory Access (DMA) with six DMA channels supporting internal and external

accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-ofblock-

transfer interrupts; and triggering from interrupt lines and all peripherals

? Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock

and output clock with skew elimination

? Hardware debugging support including On-Chip Emulation (OnCE?) module, Joint Test Action

Group (JTAG) Test Access Port (TAP)